FIR HDL Writer
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An EDA tool for generating FIR filters.   Demo
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FIR HDL Writer is an EDA tool which generates FIR filters in clear text Verilog which may be synthesized to FPGA's or ASIC's. Design options include multiple channels, coefficient sets, interpolation, decimation, and resource utilization specifications. The designs are fully synchronous and registered to provide maximum clock frequencies. Clock rates in excess of 300 MHz have been observed with Stratix II and Virtex IV devices (using Quartus and ISE synthesis and place and route tools) from Altera and Xilinx. Since verification has become a greater part of the work load for FPGA and
Requirements
  • Intel/PPC
  • Mac OS X 10.4 or later
  • Verilog Simulator for design simulation
  • Verilog Synthesizer to map the design to ASIC or FPGA



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Downloads:1,491
Version Downloads:1,491
Type:Development : Compilers
License:Demo
Date:01 Jun 2007
Platform:PPC 32 / Intel 32 / OS X
Price:Free0.00
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FIR HDL Writer is an EDA tool which generates FIR filters in clear text Verilog which may be synthesized to FPGA's or ASIC's. Design options include multiple channels, coefficient sets, interpolation, decimation, and resource utilization specifications. The designs are fully synchronous and registered to provide maximum clock frequencies. Clock rates in excess of 300 MHz have been observed with Stratix II and Virtex IV devices (using Quartus and ISE synthesis and place and route tools) from Altera and Xilinx. Since verification has become a greater part of the work load for FPGA and ASIC developers, the FIR HDL Writer includes a self checking testbenches which performs impulse, step, and random tests. The FIR HDL Writer is the first cross platform product released by Optunis, and runs natively on Windows XP, Linux, and Mac OS X.


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