FIR HDL Writer is an EDA tool which generates FIR filters in clear text Verilog which may be synthesized to FPGA's or ASIC's. Design options include multiple channels, coefficient sets, interpolation, decimation, and resource utilization specifications. The designs are fully synchronous and registered to provide maximum clock frequencies. Clock rates in excess of 300 MHz have been observed with Stratix II and Virtex IV devices (using Quartus and ISE synthesis and place and route tools) from Altera and Xilinx. Since verification has become a greater part of the work load for FPGA and ASIC developers, the FIR HDL Writer more...
- Mac OS X 10.4 or later
- Verilog Simulator for design simulation
- Verilog Synthesizer to map the design to ASIC or FPGA
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